In the fabrication of semiconductor wafers, sheet resistance has become a driving issue. This has become of particular significance in the row line formations associated with Dynamic Random Access Memory ("DRAM") devices illustrated in FIG. 1.
Sheet resistance is defined as the resistance measured across the conductive layer which is positioned atop of transistor structure. Typically, comprising tungsten silicide (WSi.sub.x) and titanium silicide (TiSi.sub.x), this layer ultimately forms the rowline of a DRAM. Standard annealing process steps in forming the conductive layer, such as tungsten silicide (WSi.sub.x), superjacent the transistor structure have yielded a sheet resistance on the order of 8 .OMEGA./.quadrature..
Sheet resistance directly correlates with propagation delay, switching speed and device size. This is supported by the principal that the lower the sheet resistance, the greater the number of electrons that will flow. Thus, the size, capacity and speed are all dependent on the electrical characteristics of the conductive layer. The following mathematical relationship exists between resistance and size: EQU R=Q*L* [1/(w.sub.c *t)]
where
R=Resistance; PA0 Q=Resistivity constant dependent on the material employed; PA0 L=Length of the conductive layer; PA0 W.sub.c =Cross-sectional width of the conductive layer; and PA0 t=Thickness of the conductive layer.
Given this equation, resistivity is inversely proportional to the thickness of the conductive layer at issue. As such, in order to lower the resistivity of the conductive layer, one solution proposed has been to increase the thickness of the layer. While this approach is theoretically feasible, it is impractical. Stress cracks can potentially form over thicker conductive layers.
Options of overcoming this stress limitation have involved using higher temperature processes in fabricating the conductive layer. Unfortunately, this higher temperature processing causes structural degradation and alters the V.sub.T for the device. As a result of this degeneration, sandwiched layers, particularly the conductive layer and the gate oxide layer of the transistor, begin to interact and leak amongst each other. Fundamentally, this is caused by the extensive time required in reaching the high temperature necessary for processing the device under this approach.
Therefore, in order to drive a larger circuit, an alternate method is required that lowers sheet resistance. Further, a method is needed that will not cause structural layers to interact, leak and contaminate amongst each other. Moreover, there is a demand for a method that will enable the feasible manufacture of faster, smaller, more powerful devices.